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Tuesday, July 28 • 3:00pm - 5:30pm
Intel Tutorial Part II: Intel-Colfax MIC Parallel Programming, Hands-on Lab CDT 102

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Colfax Developer Training (CDT) is an in-depth intensive course on efficient parallel programming of Intel Xeon family processors and Intel Xeon Phi coprocessors. The 1-day labs course (CDT 102) features hands-on exercises on the available programming models and best optimization practices for the Intel many-core platform, and on the usage of the Intel software development and diagnostic tools. The pre-requisite for this class is the one-day seminar CDT 101.
Intel Xeon Phi coprocessors, featuring the Intel Many Integrated Core (MIC) architecture, are novel many-core computing accelerators for highly parallel applications, capable of delivering greater performance per system and per watt than general-purpose CPUs. Unlike GPGPUs, they support traditional HPC programming frameworks, including OpenMP and MPI, and require the same software optimization methods as multi-core CPUs.
Hands-on Session
• Offload and Native: “Hello World” to complex; using MPI.
• Performance Analysis: VTune.
• Case Study: all aspects of tuning in the N-body calculation.
• Optimization I: strip-mining for vectorization, parallel reduction.
• Optimization II: loop tiling, thread affinity.


Tuesday July 28, 2015 3:00pm - 5:30pm CDT
Majestic G

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