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Tuesday, July 28 • 10:00am - 12:00pm
Intel Tutorial Part 1: Intel-Colfax MIC Parallel Programming Training CDT 101

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Colfax Developer Training (CDT) is an in-depth intensive course on efficient parallel programming of Intel Xeon family processors and Intel Xeon Phi coprocessors. The 1-day seminar (CDT 101) features presentations on the available programming models and best optimization practices for the Intel many-core platform, and on the usage of the Intel software development and diagnostic tools. CDT 101 is a pre-requisite for hands-on labs, CDT 102.
Intel Xeon Phi coprocessors, featuring the Intel Many Integrated Core (MIC) architecture, are novel many-core computing accelerators for highly parallel applications, capable of delivering greater performance per system and per watt than general-purpose CPUs. Unlike GPGPUs, they support traditional HPC programming frameworks, including OpenMP and MPI, and require the same optimization methods as multi-core CPUs.
Lecture Session
• MIC architecture: purpose, organization, pre-requisites for good performance, future technology.
• Programming models: native, offload, heterogeneous clustering.
• Parallel frameworks: automatic vectorization, OpenMP, MPI.
• Optimization Methods: general, scalar math, vectorization, multithreading, memory access, communication and special topics.


Tuesday July 28, 2015 10:00am - 12:00pm CDT
Majestic G

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