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Today, many new HPC systems such as Stampede are heterogeneous systems containing traditional processors, co-processors, and/or accelerators. These hardware designs for performance and efficiency greatly complicate the development of large scale applications that now require the consideration of at least three different levels of parallelism (MPI, threading, SIMD) with quite different performance considerations.
This tutorial will target application developers who are developing applications for multi- and many- core systems with a focus on the Intel Xeon Phi platform, also known as the MIC. In addition to a presentation of the programming models that are available on systems with MIC co-processors, the tutorial will provide users with hands-on guidance in using wide SIMD units through vectorization, large thread counts on each node through OpenMP, and symmetric and offload modes of execution. Accounts on Stampede will be used for the laboratory exercises.
At the completion of the tutorial, the audience will: * Have hands on experience with the use of Intel's vec-reports options. * Understand how to create arrays aligned for optimal vectorization. * Be able to create asynchronous offload codes and control data persistence on the Xeon Phi. * Understand how to properly place threads/tasks on the Xeon Phi when running in either offload or symmetric mode.
